FIGS. 28 and 29 are perspective views showing a conventional high-speed network router/server unit 50. Unit 50 includes a housing 51 that is configured to hold two system racks 52 and 53, each rack including an interconnect assembly 60 (shown in FIG. 29) made up of several active circuit cards (herein “line-cards”) 65 that are plugged into a passive “backplane” circuit board 70 (shown in FIG. 29). Within conventional interconnect assembly 60, backplane 70 functions to distribute power and card-to-card data transmissions to the various line-cards 65 connected thereto, and line-cards 65 perform various system-related communication functions.
Referring to FIG. 29, each backplane 70 is fabricated using conventional FR4 technology, and typically includes several power connectors 72 that are connected to a shared power bus 73, and several data connectors 74 that are connected to a data bus 75. Connectors 72 and 74 are pin-based connectors that facilitate manual “swapping” line-cards 65 by way of manually unplugging an older line-card, and plugging in a newer line-card. As indicated in FIG. 29, to facilitate convenient unplugging and plugging, this arrangement works best when line-cards 65 are mounted perpendicular to backplane 70.
Interconnect assemblies, such as those used in router/server unit 50, often stay in service for up to 10 years. During this time, the line-cards are typically replaced several times with newer, enhanced line-cards that typically support higher transmission speeds. While the enhanced line-cards provide some improvement in system operating speeds, the standard FR4 construction and pin-based connectors associated with conventional backplane structures typically limit card-to-card transmission speeds in these conventional interconnect assemblies to a few Gigabits-per-second (Gbps) per signal line.
Several problems must be addressed in order to provide an interconnect assembly that facilitates high (i.e., multi-Gbps per signal line) card-to-card communication speeds. For example, at high speeds, signal wavelengths become very small (i.e., the signal wavelength of a 40 Gbps signal is a few millimeter). Conventional pin-type connectors, which are fine for lower speed (i.e., long wavelength) transmissions, can easily span a substantial fraction of a wavelength when subjected to high-speed transmissions, and thus act as transmission lines. Further, signal fidelity requires controlling the characteristic impedance of the transmission line throughout its entire signal path, including all connector interfaces, properly terminating each line to avoid signal reflections, and avoiding line stubs. These requirements are difficult to meet due to the pin-based connection structures used in conventional backplanes. Moreover, the parallel data bus structure often utilized in conventional backplanes becomes unpractical because unused bus sections act as transmission line stubs. It is also very hard to maintain bus impedance without knowing where and whether line-cards are plugged in.
One solution to problems associated with conventional interconnect assemblies is to produce a backplane having point-to-point connections (i.e., where the backplane routes individual data lines from every line-card to every other line-card). However, a parallel point-to-point solution is impractical due to the large number of connections required in such a backplane. The number of point-to-point connections is lowered by adopting a serial transmission protocol, which requires fewer pins (connections) per line-card, but increases the data rates per pin accordingly. However, high data rates potentially create signal integrity problems as they call for rapid pulse fall and rise times. Quickly charging and discharging trace and input capacitances requires large transient currents that cause cross talk, ground bounce, radiation, electromagnetic interference and other signal integrity issues. Moreover, along with the ever-increasing clock rates utilized in cutting-edge systems, supply voltages continue to decrease to tame dynamic power consumption (e.g., microprocessor cores now run at 1 Volt or lower). Noise margins reduced accordingly making circuits more sensitive to signal integrity problems.
Optical fiber data transmission is therefore being used with increasing frequency. Although substantially more expensive than conventional FR4/pin-connector based assemblies, until recently fiber optic-based interconnect assemblies provided the only option for interconnect speeds of greater than 5 Gbps per data line.
A more recently developed solution involves modifying FR4-based backplanes and line card circuits to include differential signaling over copper transmission lines. This solution is simpler and potentially more economical than optical fiber-based assemblies. Perfectly balanced differential signals do not create any ground currents, and the common-mode rejection of the differential receiver cancels ground disturbances. This technique has been routinely used in interconnect assemblies at speeds of 5 Gbps per data line, and up to 10 Gbps when heroic circuit design efforts are employed. However, these differential signal interconnect assemblies appear to support a maximum transmission speed of 10 Gbps because of FR4 dielectric loss and propagation mode mismatch at the pin-based connectors.
What is needed is an interconnect assembly that overcomes the deficiencies of conventional interconnect systems, described above, and facilitates operating speeds greater than 10 Gbps.